Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs), or nonvolatile RAM and read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2). The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed.
DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications including portable devices such as laptop computers and personal digital assistants (PDAs).
SRAM is typically arranged as a matrix of thousands of individual memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows and columns so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations.
SRAM memory arrays come in all sizes from arrays having tens of cells, to arrays having billions of cells. SRAMs may also be provided as memory devices dedicated purely to memory storage operations, or as a memory array that is embedded within an integrated circuit (IC) which carries out one of a variety of other control and/or processing functions. Such embedded memory array applications may include, for example, an automotive engine controller or a communications IC, wherein the embedded SRAM memory array may store set-up parameters, coordinates, initial conditions, or other variables used by the IC. Accordingly, embedded SRAM memory array applications usually require smaller arrays than those dedicated purely to memory storage.
The basic CMOS SRAM cell generally includes two n-type or n-channel (nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up or load transistors in a cross-coupled inverter configuration, which act as a bistable latch circuit, with two additional nMOS select or pass-gate transistors added to make up a six-transistor cell (a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. A plurality of transistors are utilized in SRAM requiring matched electrical characteristics to provide predictable cell switching characteristics, reliable circuit performance, and minimize array power dissipation.
Each inverter of the SRAM memory cell includes a load transistor and a driver transistor. The output of the two inverters provide opposite states of the latch, except during transitions form one state to another. The pass-gate transistors provide access to the cross-coupled inverters during a read operation (READ) or write operation (WRITE). The gate inputs of the pass transistors are typically connected in common to a word line (wordline or WL). The drain of one pass transistor is connected to a bit line (bitline or BL), while the drain of the other pass transistor is connected to the logical complement of the bit line (bitline-bar or BLB).
A WRITE to a 6T cell is enabled by asserting a desired value on the BL and a complement of that value on BLB, and asserting the WL. Thus, the prior state of the cross-coupled inverters is overwritten with a current value. A READ is enabled by initially precharging both bitlines to a logical high state and then asserting the WL. In this case, the output of one of the inverters in the SRAM cell will pull one bitline lower than its precharged value. A sense amplifier detects the differential voltage on the bitlines to produce a logical “one” or “zero,” depending on the internally stored state of the SRAM cell.
Accordingly, a consideration in the design of the embedded SRAM memory array is the leakage current of the cell transistors, which can be a significant contributor to the total power consumption of the device. The total leakage current of the device may be expressed as the supply current of the device (Idd) in the quiescent state or IDDQ. In a prior art, the memory can be put into a low power retention mode by reducing the voltage across the cell, but at minimum retention voltage, the cell can not be accessed for READ or WRITE operations in a normal manner. This is because the static noise margin (SNM), the trip voltage (Vtrip), and the read current (Iread) of the cell are all reduced. A reduced SNM can lead to cell upsets during READ or to unaccessed columns in an accessed row during WRITE. Therefore, there is overhead in latency and power when going into or out of the retention mode. As a result, such power consumption overhead and operational time delays are counterproductive to the goals of modern integrated circuits and embedded memory devices.
Accordingly, there is a need for an improved SRAM memory and method of operation that permits a low quiescent supply current while allowing some functionality, substantially maintains the static noise margin, trip voltage, and read current of the SRAM device, yet minimizes data upsets, latency, and switching power overhead in SRAM memory devices.